Currently methods for programming or writing of non-volatile memory cells fall into two categories. They are
a) The EEPROM write. PA1 b) The EPROM write. PA1 1. Need for generating a high field across the tunnel oxide by applied voltage alone makes application of high voltages necessary. PA1 2. The tunneling is a process which is proportional to the applied field and slows down as the floating gate gets charged. PA1 3. The slow charging of the floating gate with the changing field across the tunnel oxide also makes it necessary to have a high enough voltage on the floating gate initially to achieve sufficient voltage differential at the end of programming between the two sense levels during read. PA1 4. Tunneling process is slow, as carriers have to be generated by breaking silicon bonds and providing sufficient energy to tunnel, and typically take anywhere from 1 to 10 mil seconds to reach completion. PA1 1. EPROM write uses high voltage and high current to produce the hot electrons at the drain depletion hence needs high voltage, high current supplies. PA1 2. High gate voltages are used on the gate to collect the carriers. PA1 3. The hot electron write process is much faster than tunneling but is still slow compared to other types of memories, typically needing over 10 micro-seconds. PA1 4. The high fields used reduce the device reliability. PA1 5. During the hot electron generation by impact ionization, a large volume of positively charged carriers is also generated which needs to be removed through the substrate to prevent reliability problems with the circuit. PA1 1. The method by virtue of using the energy available in the velocity of the carriers in the channel, in the form of kinetic energy, is able to effectively reduce the barrier height of the oxide separating the channel from the floating gate, allow lower voltage to be used on the floating gate during write. This allows for reduction in control gate voltage from those used in prior art cells.
a) The EEPROM write
This method of writing or programming a non volatile memory involves application of a high potential gradient across a thin oxide designated tunnel oxide which has a thickness of the order of 50 to 150 Angstroms. The potential gradient is applied by directing a high voltage to the nodes on either side of the oxide barrier. If a sufficiently high potential gradient can be established, typically of the order of 1 MV/cm of oxide thickness, then electrons in the silicon can be provided enough energy to overcome the potential barrier of the oxide and reach the positive floating or storage node by tunneling. These electrons charge the electrode to a negative potential and allow modification of the threshold of a device, allowing the possibility of data storage.
FIG. 1 shows the typical EEPROM cross section. A diffused region (3) with n-diffusion is disposed trader a thin tunnel oxide region (2) typically having a thickness of 50 to 150 A. A first floating gate conductive material (5), typically doped poly silicon is disposed over the tunnel oxide and also extends over a gate oxide (8) disposed over a channel region of an MOS device. A second conductive layer (6), typically a doped polysilicon, over lays the floating gate and is separated from the floating gate by an insulating layer (7), typically oxide or ONO. The second conductive layer acts as the control gate. During write the diffused region (3) is held at ground voltage while a high voltage, typically ranging from 12 to 22 V, is applied to the control gate. This high voltage gets capacitively coupled down to the floating gate. The voltage to which the floating gate is raised depends on the coupling ratio Cx=Cpp/Ctot, where Cpp is the poly to poly capacitance and Ctot is the total capacitance on the floating gate. This floating gate voltage appears across the tunnel oxide. By applying a sufficiently high voltage on the control gate, to provide a high field across the tunnel, carriers can be made to tunnel across from the diffused region to the floating gate. The applied high voltage is limited by the break down voltage of the tunnel and inter poly insulator. In most EEPROM a select device (12) in series with the storage device is used to isolate the storage device during write.
The typical resultant field directions in an EEPROM during write are shown in FIG. 2. As can be seen the field "Fe" due to the applied high voltage HV which influence the tunneling process in an EEPROM is in a direction perpendicular to the tunnel oxide and into the floating gate.
Main disadvantages of EEPROM write method are:
b) The EPROM write:
EPROM write is a method of writing the non volatile memory in which the high saturated velocity of the electrons in the high field depletion area, produced by application of a high drain voltage, typically from 5.5 to 9 V, of an MOS device in saturation is used to generate a large volume of high energy carriers or hot electrons by impact ionization, of which a proportion having the correct energy levels is provided enough additional acceleration by a high voltage, typically of the order of 5.5 to 10 V applied to a floating electrode to overcome the barrier and get collected by it. The fields at the drain depletion which support the carrier generation is improved by higher drain voltages and higher gate oxide thicknesses, since the devices have to be in saturation. A higher drain voltage and gate voltage is also necessary to provide sufficient number of electrons in the channel to generate the volume of impact ionized carriers necessary for complete write. The high volume of the carriers generated ensures that even the small percentage collected by the floating gate is sufficient to provide a reasonably large swing in threshold of the MOS device.
FIG. 3 is the cross sections of a typical EPROM. AMOS channel is formed under a gate oxide (6) on a doped substrate (1) between a source region (4), doped with an impurity of the opposite type to the substrate, and a doped drain region (3), doped similar to the source. Overlying the gate oxide is a conductive floating gate electrode (7), typically formed by a doped polysilicon layer. A second conductive layer(9), typically a doped polysilicon layer, overlying the floating gate layer and separated from it by an insulating layer (8), typically oxide or ONO, forms a control gate. During write a high voltage, typically in the range of 10 to 15 V is applied, to the control gate which gets capacitively coupled down to the floating gate raising the floating gate voltage. A high drain voltage is applied to conduct a high current and also take the device into saturation. This forms a high field in the drain depletion region where impact ionization generates a large carrier concentration having high energies. The voltage on the floating gate, from the coupled down high voltage on the control gate, provides the additional energy to allow acceleration and collection of a small percentage of the generated hot electrons by the floating gate. The write process is faster than the tunneling process, typically taking 10 to 100 micro seconds only.
The fields applied and the resultant field in an EPROM write is shown in FIG. 4. The force on a carrier in an EPROM during programming, due to the carrier velocity and the voltage(Vd) applied to the drain (3), tend to oppose that due to the voltage (C.HV) on the storage electrode(7) coupled down from the control electrode (9).
Major disadvantages of EPROM write method with hot electrons: